Modifying FPGA image of USRP

Motivation

I attended some sessions in the conference (COCORA 2014) in Nice, France. I had the chance to talk to the speakers in the panel that focused on Software Defined Radio (SDR). I was presenting the topic of improving the role of FPGA in OpenBTS project. OpenBTS is an open source GSM network based on the Universal Software Radio Peripheral (USRP). Unlike me, most of the speakers focused on applications of cognitive radio at high level. They adopted the idea that "for FPGA, what is done is done". Well, our team see a lot of opportunities in modifying the FPGA Code.

Modifying FPGA Image Steps

1. Install Xilinx ISE 14.1 (12.1 or any compatible version).
2. Get the source files of the universal hardware driver (UHD) using the "git" shell command . If you need more details, see the following instructions. 
   

    git clone git://github.com/EttusResearch/uhd.git 

3. The "git" command will retrieve the latest stable version. The current version is UHD-Mirror-release_003_007_001. The downloaded source files will have the following structure:

4. Inside the folder "fpga" we can modify any part of the FPGA code for different USRPs. In this example, we will modify the top module of E100 which is located at the following path:
   

   ~/fpga/usrp2/top/E1x0/u1e_core.v

5. Install OpenBTS either on Windows or Linux operating system as you prefer. In addition, download the source code for OpenBTS. Now, our goal is to move a function called "AnalyzeTrafficBurst" from C file to Verilog
   

   from C : ~/openbts_4.0.0/openbts/Transceiver52M/sigProcLib.cpp
   Into Verilog : ~/fpga/usrp2/top/E1x0/u1e_core.v

6. Before we determine where to place the moved function into the Verilog code, we need to understand the general architecture of the FPGA code. Therefore, a high level block diagram was constructed which shows the main modules that forms the FPGA functionality, and the connections between the modules. The FPGA communicates with the processor using GPMC wishbone as shown in the figure below. There exist one wishbone master and 8 slaves.

   

   Right click + Open in New Tab for signals' names

7. In the diagram below we detail the connections of the wishbone master GPMC, to understand how the signal is converted from the antenna and transmitted to the processor. Data from ADC is concatenated with 4 zeros. Then decimated through the module ddc_chain0 or ddc_chain1 based on application needs (1 receiver or 2 receivers). The transmission protocol is the VITA protocol which is handled by the block vita_rx_chain. Then the multiplexer is used to combine the two streams and forward them to the wishbone master (GPMC).

   

   Right click + Open in New Tab for signals' names

   
   
8. After we have explored the hierarchy of the code, any module can be easily understood, such as ddc_chain0, by locating its code in the project. Now, it is time to insert the function "Anaylze Traffic Burst" after we have converted it from  C code into Verilog code. It will be added before the GPMC bus as shown below. If you understood the previous hierarchy, you can observe how the hierarchy is perfectly mapped to Verilog code.
   
9. To build (synthesize) the code navigate to the folder "~\fpga\usrp2_compt9\top\E1x0", then use the make file in your terminal
   

     make E100

10. When the build is complete, a folder will be created named "build-E100". Although we use tcl script to build the code, it is convenient to open the GUI to check for the project hierarchy. Below you can see the instance AnalyzeTrafficBurst has been injected into the code.
    
11.  Last step is to copy the generated binary image u1e.bin from the folder build-E100 into /usr/share/bin/images. Now, you can run the application and compare the performance before moving the function AnalyzeTrafficBurst to FPGA and after it.

To conclude, we are able to modify the FPGA image which is used on the embedded series E100 and E110 of ETTUS software defined radio platforms. Please, contact me if there are steps that are not clear, so I can give more illustration. Thank you!   


References

[1] UHD
[2] O. Sekkat, “Usrp Fpga Exploration”